The flip chip packaging technology was introduced by IBM in the early 1960s, and this technology differs from the wire bonding technology in that the electrical connectivity between the semiconductor chip and the substrate is achieved by the solder bump instead of the conventional wires. The main advantage of the flip chip packaging technology lies in its capability of elevating packaging density, thus the size of the packaged components are reduced; on the other hand, the flip chip packaging technology does not require wires of longer length, and hence the electrical functionality can be improved. As a result, the industry has been employing high-temperature soldering on ceramic substrates for years, and this technology is termed as control-collapse chip connection or 4C technology. Because the demand for semiconductor components of high-density, high-speed, low-cost has increased dramatically, and a trend that calls for smaller electronic products has emerged; it has become common to place the flip chip components on a low-cost organic circuit board (for example, a printed circuit board or a substrate board), then followed by the filling of epoxy underfill resin underneath the chip in order to minimize the thermal stress resulted from the differences in thermal expansion between silicon chip and organic circuit board structure, and the phenomenon has grown exponentially.
In the current flip chip packaging technology, the surface of semiconductor integrated circuit chip is disposed an electrode pad thereof, and its corresponding connecting pad is disposed on the organic circuit board; a solder bump or other conductive solder materials is filled between the chip and the circuit board, so that the chip is disposed on the circuit board with its electrical connecting side facing downwards. The solder bump or the conductive adhesive material used in this technology provides for the electrical input and output, as well as the mechanical connection between the chip and the circuit board.
Moreover, when the circuit board and the semiconductor chip are to be packaged, a plurality of solder balls are required to be implanted on the bottom surface of the circuit board, so that it is possible for the circuit board to electrically connect to external electronic devices. In order to allow the solder balls to connect to the circuit board effectively, the electrical connection pads of the circuit board that are to be used for the disposition of solder balls must be formed with the soldering material for connecting the solder balls first.
Currently, the method that is most commonly used to form soldering material on the electrical connection pads of the circuit board is the stencil printing technology. However, the developmental trend of miniaturization for semiconductor chip is driving changes in the semiconductor packaging technology, in order to allow the ever-shrinking chips to have more input and output terminals. But the change also shrinks the total area of carried components in a chip, which in turn increases the quantity of electrical connection pads on the carried components; as a result, the demands for the development of chip can only be satisfied by shrinking the size and the pitch of electrical connection pads. But the shrinking of electrical connection pads also makes the openings on the stencil used in stencil printing technology smaller as well. As a result, the smaller openings on stencil not only increases the cost for producing the stencil, which is resulted from difficulty in stencil production; but also hampers the later production process because the smaller opening on the stencil can be impervious to the soldering material. Furthermore, apart from the requirement of accurate size of stencil in order to ensure the precision in the shaping of soldering material; there are the problems of the number of times the stencil has been used and cleaned. Since the soldering material is viscous, it can stick to the inner wall of openings in the stencil and accumulate as the stencil is used to print many times, and this can give rise to incorrect quantity and shape of soldering material from the design specification when the stencil is used next time. Therefore, when the stencil is put to actual usage, it must be cleaned after a certain times of printing, otherwise problems like conflicting shape and size of soldering material can arise and result in the production process being impeded, which lowers its reliability.
To solve the forgoing problem, a method for fabricating a conductive bump on the electrical connection pad of the circuit board via electroplating has been employed.
FIGS. 1A to 1K, are cross-sectional views of a convention electrical connection structure of circuit board fabricated via electroplating and in accordance with the prior-art.
As shown in FIG. 1A, a first conductive layer 10 is formed on an insulating layer 11 of the circuit board. The first conductive layer 10 can be formed by chemical deposition or sputtering, and is also referred as a seed layer. Referring to FIG. 1B, a first resist layer 12 is formed on surface of the first conductive layer 10, and a plurality of first openings 120 are formed on the first resist layer 12 via patterning processes such as exposure and developing, so as to expose the conductive layer 10. Generally, the first resist layer 12 is made of photosensitive material such as a dry film. Referring to FIG. 1C, an electrical connection pad 13 is formed in the first openings 120 via electroplating. Referring to FIG. 1D the first resist layer 12 is removed by stripping. Referring to FIG. 1E, the first conductive layer 10 is removed by chemical etching. Referring to FIG. 1F, a solder mask layer 14 is formed over the surface of the circuit board. The solder mask layer 14 is made of photosensitive materials. Further, a plurality of second openings 140 are formed at positions corresponding to the electrical connection pads 13 via patterning processes such as exposure and developing, so as to expose the electrical connection pads 13. Referring to FIG. 1G, a second conductive layer 15 is formed by chemical deposition or sputtering of the solder mask layer 14 and surfaces of exposed portion of electrical connection pads 13, wherein the material and property of the second conductive layer 15 is as same as that of the first conductive layer 10. Referring to FIG. 1H, a second resist layer 16 is formed on the surface of the second conductive layer 15, wherein the material and property of the second resist layer 16 is as same as that of the first resist layer 12. Accordingly, a plurality of third openings 160 are formed at positions corresponding to the electrical connection pads 13 via patterning processes such as exposure and developing, so as to expose a portion of the second conductive layer 15. Referring to FIG. 1I, a metal bump 17 is formed in the third openings 160 via electroplating; and generally the metal bump 17 is made of solder materials which can form an electrical connecter of the circuit board for connecting a semiconductor chip or a passive component. Referring to FIG. 1J, the second resist layer 16 is removed by stripping. Referring to FIG. 1K, the exposed portion of the second conductive layer 15 is removed via chemical etching.
Although problem of stencil printing technology known in prior-art can be solved via the forgoing method of electroplating, the size of the openings of the solder mask layer and electroplating resist layer are formed via exposure and developing, which have to be performed precisely and accurately. As the range of alignment accuracy of a general machine is approximately 20 μm-30 μm, it is difficult to align the openings of the electroplated resist layer with the center of the opening of the solder mask layer. Accordingly, the size of the openings has to be increased in order to reduce the difficulty of alignment. Nevertheless, the requirement of forming fine pitches between the electrical connection pads cannot be met if the openings of the electroplated resist layer are enlarged.
Therefore, the conductive bumps cannot be formed on the electrical connection pads having fine pitches therebetween by the electroplating process. Moreover, if the conductive bumps are to be formed with fine pitches therebetween, the insulating layer and resist layer have to be aligned more accurately, resulting to a increase of complexity of fabrication, fabrication time and difficulty of alignment. Furthermore, in the processes of the aforementioned fabrication, the solder mask layer is formed first on the circuit board. Then a patterned resist layer is formed on the solder mask layer. Subsequently, an electroplating process is performed to form solder materials. Later, the resist layer is formed on the solder mask layer. However, due to foregoing fabrication processes, the volume of the overall structure will become too thick, and thus increases difficulty of electroplating process. Moreover, if the solder material is formed directly on the electrical connection pads in the openings of the solder mask layer, the heights of the solder materials of the electrical connection pads are difficult to control, and thus results in forming rough surfaces with uneven height of conductive bumps and making a serious impact on reliability of forming electrical connections between circuit boards and external electrical elements subsequently.